The present invention relates to a semiconductor device in which an FET (field effect transistor) with a MIS (Metal/Insulator/Semiconductor) structure is formed in an element region defined by trench isolation.
In recent years, as element isolation for a semiconductor integrated circuit, not the conventional element isolation using selective oxidation but so-called trench isolation wherein a trench is formed in a semiconductor substrate and an insulating film is buried in the trench to form an element isolation region is used. In this trench isolation, the bird's beak that is a problem in selective oxidation (LOCOS) is small, and the breakdown voltage can be kept satisfactory even when the element isolation width is small. Hence, the degree of integration can be increased.
However, in a MISFET formed by the conventional trench isolation process, the threshold voltage of side portions on both sides in the channel width direction undesirably becomes low. This is because when the surface layer is cleaned and exposed in the previous step of forming a gate insulating film on the surface of the semiconductor layer, the gate electrode is readily partially formed at a level lower than the interface between the semiconductor substrate and the gate insulating film.
FIG. 15A is a sectional view showing the structure of a conventional MISFET. Referring to FIG. 15A, the MISFET has a semiconductor substrate 10, element isolation trench 11 formed around an element region, insulating film 14 formed on the inner wall of the trench 11, insulating film 15 buried in the trench 11, impurity-implanted region 17, gate insulating film 18, and gate electrode 19. Although not illustrated, source and drain regions are formed on the major surface of the substrate 10 on both sides of the channel region underneath the gate electrode 19.
The major surface of the element region is almost flat. However, the end portions near the periphery of the trench (on both sides in the channel width direction) have tilt surfaces which are inevitably formed due to the manufacturing process. More specifically, to form the trench 11, a buffer layer and etching stopper film are deposited on the substrate 10. After a pattern is formed on these layers, a trench having a depth of 0.1 to 2 .mu.m is formed in the substrate 10. Next, the substrate 10 is annealed in an oxygen atmosphere to form the silicon oxide film 14 having a thickness of 5 to 100 nm in the trench 11. During formation of this oxide film 14, oxidation of the silicon substrate 10 progresses from the surface of the sides due to oxidation species such as oxygen or H.sub.2 O entering the buffer layer. For this reason, the buffer layer becomes thicker at the trench side wall than at the flat portion to form a bird's beak, and a tilt surface due to the bird's beak is formed on the upper surface of the side portions of the element region.
Referring to FIG. 15A, a dotted line 20 represents the lower end of the channel depletion layer when the threshold voltage is applied to the gate electrode. La and Lb represent vertical distances (depths) from the interface between the gate insulating film 18 and the substrate 10 to the depletion layer end, which are measured in the vertical direction with respect to the major surface of the substrate. La is the depth at the flat substrate portion (main portion), and Lb is the depth at the tilt substrate portion (side portion) along the periphery of the trench. In the conventional process of implanting channel ions to a portion near the interface, when the bird's beak at the edge of the buffer layer is small, a channel ion profile is formed to a predetermined depth from the interface between the gate insulating film 18 and the substrate 10.
Prior art 1 will be described next in detail in which the threshold voltage lowers in the arrangement shown in FIG. 15A. FIG. 15B is an enlarged view of a side portion Sc in FIG. 15A. Assume that the gate insulating film 18 has a uniform film thickness at the flat substrate portion and at the side portion along the periphery of the trench, or the gate insulating film 18 becomes thin at the side portion. In this case, as shown in FIG. 15B, the side portion of the substrate 10 is surrounded by the gate electrode 19 via the gate insulating film 18 at the upper and side surface portions. For this reason, the electric field from the electrode 19 concentrates in the side portion rather than in the main portion. When the gate insulating film 18 is thin at the side portion, field concentration is more noticeable.
In the conventional structure shown in FIG. 15B in which the distances La and Lb are almost equal, the substrate 10 is depleted from the side surface at the side portion due to the electric field from the side surface. For this reason, charge share of depletion layer charges from the semiconductor substrate surface decreases in correspondence with the depletion layer. The threshold voltage of the MISFET at the side portion becomes lower than that of the MISFET at the main portion, resulting in a parasitic side transistor. A line PL in FIG. 15B indicates the position of the peak of the dopant concentration in the channel region.
FIG. 16A shows prior art 2 in which the threshold voltage is prevented from becoming lower even when a gate electrode 19 is partially formed at a level lower than the upper surface of a semiconductor substrate 10. This structure has been discussed in, e.g., Tai-Su Park, Yu Gyun Shin, Han Sin Lee, Moon Han Park, Sang Dong, Kwon, Ho Kyu Kang, Young Bum Koh, and Moon Yong Lee, International Electron Devices Meeting Technical Digest, 1996, pp. 747-750, FIG. 11A. The film structure other than the channel profile structure is known.
In prior art 2, the tilt surface of the side portion of the element region is wider. An insulating film 14 also remains on this tilt surface. This structure is preferable not to form any parasitic transistor having a low threshold voltage at the side portion. In this case, at a portion where the insulating film 14 is formed on the tilt surface, the channel impurity having its maximal concentration value near the surface stays in the insulating film 14 without entering the substrate 10. Hence, the concentration on the surface is lower at the side portion of the element region than at the main portion.
FIGS. 16B and 16C are enlarged views of a side portion Sc between a gate electrode 19 and the substrate 10. A dotted line 20 indicates the channel depletion layer end. La and Lb represent depths from the interface between a gate insulating film 18 and the substrate 10, which are measured in the vertical direction with respect to the major surface of the substrate. La is the depth at the flat semiconductor substrate portion (main portion), and Lb is the depth at the side along the periphery of the trench. A line PL in FIGS. 16B and 16C indicates the position of the peak of the dopant concentration in the channel region.
In prior art 2, the insulating film 14 is formed in advance on the tilt surface of the side portion. Referring to FIG. 16B, at the side portion of the semiconductor substrate along the periphery of the trench, which is covered with the insulating film 14, the insulating film sandwiched by the gate electrode 19 and semiconductor substrate 10 can be made thicker than the gate insulating film 18. More specifically, the insulating film 14 at the side portion is formed thicker than the gate insulating film 18 at the main portion such that the insulating film 14 is left at the side portion. In this state, the gate insulating film 18 is formed. With this process, the insulating film 14 thicker than the gate insulating film 18 is formed at the side portion between the gate electrode 19 and the substrate 10. In the region covered with the insulating film 14, a parasitic transistor with a low threshold voltage is hard to form.
On the other hand, at the side portion not covered with the insulating film 14, the threshold voltage becomes low. A structure that does not lower the threshold voltage will be described first, and then, a structure that lowers the threshold voltage will be described.
In FIG. 16B, Le is the thickness of the gate insulating film at the side portion, and Ld is the thickness of the gate insulating film 18 at the main portion. When the thickness of the gate insulating film at the side portion almost equals that at the main portion, Ld almost equals Le. Especially, in prior art 2, the insulating film 14 readily remains on the side-portion tilt surface, as shown in FIG. 16B. Preferably, the gate insulating film at the side portion becomes thicker due to the remaining insulating film 14, to satisfy Le&gt;Ld.
Where Q.sub.B is the absolute value of charges of acceptors in the semiconductor substrate 10, .epsilon. is the permittivity of the gate insulating film 18, t is the thickness of the gate insulating film 18, V.sub.FB is the work function difference between the gate electrode 19 and the substrate 10, and 2.phi..sub.F is the inversion potential, a threshold voltage V.sub.th of the transistor is given by EQU V.sub.th =V.sub.FB +2.phi..sub.F +Q.sub.B.multidot.t.epsilon. (1)
This reveals that as the gate insulating film thickness t increases, the threshold voltage V.sub.th becomes high even when the value Q.sub.B does not change. The value Q.sub.B is determined by the substrate profile and substrate bias and does not depend on the gate insulating film thickness. For this reason, when the gate insulating film at the side portion becomes thicker than that at the main portion, the threshold voltage at the side portion rises to prevent any side parasitic transistor.
Especially, when the thickness Le is sufficiently larger than the thickness Ld, the so-called surface potential at the interface between the gate insulating film 18 and the substrate 10 increases at the side portion rather than at the main portion. Hence, as shown in FIG. 16B, the depletion layer width Lb at the side portion is smaller than the depletion layer width La at the main portion.
FIG. 16C illustrates the side portion Sc when the insulating film 14 rarely remains on the side-portion tilt surface of the conventional structure shown in FIG. 16A, and the gate insulating film becomes thinner at the side portion. In this case, the gate insulating film at the side portion has a thickness equal to or smaller than that at the main portion. When Le&lt;Ld, the threshold voltage at the side portion becomes low from equation (1).
Especially, in a region 17 of prior art 2, where the substrate impurity profile has an impurity peak on the surface, the threshold voltage at the side portion further drops. Since the implantation depth is smaller at the side portion than at the main portion because of the insulating film 14, ions are implanted closer to the surface. FIG. 17 shows the impurity profile at the main portion along a line Pf-Pf' and that at the side portion along a line Pg-Pg' in FIG. 16C. Pf and Pg indicate the interfaces between the gate insulating film 18 and the substrate 10 at the main and side portions, respectively. Pf' and Pg' indicate the channel depletion layer ends at the main and side portions, respectively.
Ions implanted in the surface portion of the impurity profile at the main portion do not remain in the substrate 10 at the side portion. For this reason, the substrate impurity concentration becomes low near the surface at the side portion, and the impurity amount at the side portion of the ion-implanted region 17 becomes smaller than that at the main portion. At the side portion, the depletion layer expands to result in La&lt;Lb. Since the impurity concentration at the depletion layer end becomes lower as the depth increases, the value Q.sub.B at the main portion is smaller than that at the side portion. Hence, the threshold voltage at the side portion more easily becomes low.
In prior art 2, the process is complicated because a process of forming the sacrificial insulating film for ion implantation and removing the insulating film is necessary. When the sacrificial insulating film is formed by oxidizing or nitriding the substrate 10, the main portion of the substrate 10 is oxidized or nitrided and retreats from the side portion protected by the buffer layer. This readily results in La&lt;Lb, and the threshold voltage easily lowers. In prior art 2, since the side-portion tilt surface is covered with the insulating film 15, channel ions are not implanted into the semiconductor substrate 10 of the tilt surface. For this reason, the threshold voltage at the side portion more easily drops.
FIG. 18 shows the structure of prior art 3 for preventing the threshold voltage from dropping at the side portion. In this structure, boron or indium is implanted at a dose of 10.sup.12 to 10.sup.16 cm.sup.-2 and an acceleration energy of 1 to 300 keV to form a region 21 where the acceptor impurity concentration on the trench side surface is increased. This increases the substrate impurity concentration at the side portion and increases Q.sub.B of equation (1). Hence, the depletion layer width at the side portion can be made smaller than that at the main portion, and the threshold voltage V.sub.th can be increased.
In the manufacturing process of prior art 3, however, the number of steps of channel ion implantation increases. Especially, for transistors having a plurality of conductivity types in, e.g., a CMOS circuit, ions with the same conductivity type as that of each well must be implanted into the well. To do this, after a trench region is formed, a resist is applied to the trench region, and lithography is performed to form a mask for ion implantation. In this case, since the resist comes into contact with a portion near the inner wall of the trench, impurity contamination due to organic substances or metals from the resist to the trench poses a problem.
When a MISFET is formed, the heavily doped region 21 of the well comes into contact with heavily doped source and drain regions which have a conductivity type opposite to that of the well. For this reason, the depletion layer capacitance of the source and drain regions increases to increase the tunnel leakage current from the junction. In addition, to implant ions of a sufficient dose into the side surface, a dose twice or more that of channel ion implantation is needed. Hence, defects due to ion implantation on the wall and bottom surfaces of the trench pose a problem.
As described above, in the conventional semiconductor element isolation structures, the element isolation insulating film is etched to a level lower than that of the semiconductor region because of the previous step of channel ion implantation and the previous step of gate insulating film formation in forming a MISFET. When the gate insulating film becomes thin at the side portion, a parasitic transistor having a low threshold voltage forms at the side portion of the semiconductor region.